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1. general description the TJA1029 is the interface between the loca l interconnect network (lin) master/slave protocol controller and the physical bus in a lin network. it is primarily intended for in-vehicle subnetworks using baud rates up to 20 kbd and is compliant with lin 2.0, lin 2.1, lin 2.2, lin 2.2a and sae j2602. the tj a1029 is pin-compatible with the tja1020, tja1021, tja1022 and tja1027. the protocol controller generat es the transmit data stream. the TJA1029 converts the data stream into an optimized bus signal shaped to minimize electromagnetic emissions (eme). the lin bus output pin is pulled high via an internal termination resistor. for a master application, connect an external re sistor in series with a diode between pin v bat and pin lin. the receiver detects a receive data stream on the lin bus input pin and transfers it via pin rxd to the microcontroller. power consumption is very lo w in sleep mode. however, th e TJA1029 can still be woken up via pins lin and slp_n. an integrated tx d dominant time-out fu nction prevents the bus being driven to a permanent dominant state. 2. features and benefits 2.1 general ? compliant with lin 2.0, lin 2.1, lin 2.2, lin 2.2a and sae j2602 ? baud rate up to 20 kbd ? very low electromagnetic emissions (eme) ? very low current consumption in sleep mode with remote lin wake-up ? input levels compatible with 3.3 v and 5 v devices ? integrated termination resistor for lin slave applications ? passive behavior in unpowered state ? operational during cranking pulse: full operation from 5 v upwards ? undervoltage detection ? k-line compatible ? available in so8 and hvson8 packages ? leadless hvson8 package (3.0 mm ? 3.0 mm) with improved automated optical inspection (aoi) capability ? dark green product (halogen free and rest riction of hazardous substances (rohs) compliant) ? pin-compatible subset of the tja1020, tja1021 and tja1022 ? pin-compatible with the tja1027 TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout rev. 1 ? 8 january 2013 product data sheet
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 2 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 2.2 protection ? very high electromagnetic immunity (emi) ? very high esd robustness: ? 8 kv according to iec 61000-4-2 for pins lin and v bat ? bus terminal and battery pin protected against transients in the automotive environment (iso 7637) ? bus terminal short-circuit proof to battery and ground ? thermally protected ? initial txd dominant check when switching to normal mode ? txd dominant time-out function 3. quick reference data 4. ordering information table 1. quick reference data symbol parameter conditions min typ max unit v bat battery supply voltage limiting values ? 0.3 - +42 v operating range 5 - 18 v i bat battery supply current sleep mode; v lin = v bat ; v slp_n = 0 v 2.5 7 10 ? a standby mode; v lin = v bat ; v slp_n = 0 v 2.5 7 10 ? a normal mode; v lin = v bat ; v slp_n = 5 v; v txd =5 v 200 800 1600 ? a v lin voltage on pin lin limiting value; with respect to gnd and v bat ? 42 - +42 v v esd electrostatic discharge voltage on pin lin; according to iec 61000-4-2 ? 8-+8kv t vj virtual junction temperature ? 40 - +150 ?c table 2. ordering information type number package name description version TJA1029t so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1 TJA1029tk hvson8 plastic thermal enhanced ve ry thin small outline package; no leads; 8 terminals; body 3 ? 3 ? 0.85 mm sot782-1
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 3 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 5. block diagram fig 1. block diagram bus timer power-on reset and undervoltage detection v bat lin gnd 015aaa345 6 5 temperature protection control TJA1029 slp_n txd 2 4 rxd 1 7 dom timer
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 4 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 6. pinning information 6.1 pinning 6.2 pin description [1] for enhanced thermal and electrical performance, so lder the exposed center pad of the hvson8 package to board ground and not to any other voltage level. a. TJA1029t: so8 package b. TJA1029tk: hvson8 package fig 2. pin configuration diagrams TJA1029t rxd n.c. slp_n v bat n.c. lin txd gnd 015aaa356 1 2 3 4 6 5 8 7 txd 4 n.c. 3 slp_n 2 rxd 1 gnd 5 lin 6 v bat 7 n.c. 8 015aaa357 TJA1029tk terminal 1 index area transparent top view table 3. pin description symbol pin description rxd 1 receive data output (open-drain); active low after a wake-up event slp_n 2 sleep control input (active low); resets wake-up request on rxd n.c. 3 not connected txd 4 transmit data input gnd 5 [1] ground lin 6 lin bus line input/output v bat 7 battery supply n.c. 8 not connected
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 5 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 7. functional description the TJA1029 is the interface between the lin master/slave protocol controller and the physical bus in a lin network. according to the open system interconnect (osi) model, this interface makes up the lin physical layer. the lin transceiver is optimized for, but no t limited to, automoti ve applications with excellent electromagnetic compatibility (emc) performance. 7.1 lin 2.x/sae j2602 compliant the TJA1029 is fully lin 2.0, lin 2.1, lin 2.2, lin 2.2a and sae j2602 compliant. the lin physical layer is independent of higher osi model layers (e.g. the lin protocol). consequently, nodes containing a lin 2.2a-compliant physical layer can be combined, without restriction, with lin physical laye r nodes that comply with earlier revisions (lin 1.0, lin 1.1, lin 1.2, lin 1. 3, lin 2.0, lin 2.1 and lin 2.2). 7.2 operating modes the TJA1029 supports modes for normal ope ration (normal mode) and very-low-power operation (sleep mode). an intermediate wake-up mode between sleep and normal modes is also supported (standby mode). the state diagram is shown in figure 3 .
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 6 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout [1] the TJA1029 enters sleep mode after a power-on reset (e.g. after switching on v bat ). [2] the TJA1029 switches automatically to standby mode when a lin wake-up event occurs in sleep mode. [3] the wake-up interrupt (on pin rxd) is released after a positive edge on pin slp_n. [4] a positive edge on slp_n triggers a transition to norm al mode. the transmitter will be off if txd is low and will be enabled as soon as txd goes high. (1) a positive edge on slp_n triggers a transition to normal mode. the transmitter is enabled when txd goes high. in the event of thermal shutdown, the transmitter is disabled. fig 3. state diagram table 4. operating modes mode slp_n rxd transmitter description reset x floating off all inputs ignored; all outputs drivers off sleep [1] 0 floating off no wake-up request detected standby [2] 0low [3] off wake-up request detected normal 1 high: recessive state low: dominant state normal mode [4] bus signal shaping enabled 015aaa215 t (slp_n = 1) > t gotonorm t (slp_n = 1) > t gotonorm t (slp_n = 0) > t gotosleep t (lin = 01; after lin = 0) > t wake(dom)lin falling v bat < v th(por)l normal rxd: data output transmitter: on (1) standby rxd: low transmitter: off sleep rxd: floating transmitter: off reset rxd: floating transmitter: off rising v bat > v th(por)h
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 7 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 7.2.1 reset mode when the TJA1029 is in reset mode, it ignores all input signals and all output drivers are off. the TJA1029 switches to reset mode when the voltage on v bat drops below the low-level power-on reset threshold, v th(por)l . when the voltage on v bat rises above the high-level power-on reset threshold, v th(por)h , the TJA1029 switches to sleep mode. 7.2.2 sleep mode the TJA1029 consumes significantly less pow er in sleep mode than in normal mode. even though curr ent consumption is extremely low in sleep mode, the TJA1029 can still be woken up remotely via pin lin or activa ted directly via pin slp_n. filters on the receiver input (lin) and on pin slp_n prevent unwanted wake-up events occurring due to automotive transients or radio frequency interference. all wake-up events must be maintained for a specific period (t wake(dom)lin or t gotonorm ). a falling edge on pin slp_n in normal mode initiates a transition to sleep mode. the lin transmit path is immediately disabled when pin slp_n goes low. in order to ensure the TJA1029 switches successfully to sleep mo de, the sleep command (pin slp_n = low) must be maintained for at least t gotosleep . sleep mode activation is independent of the leve ls on pins lin or txd. so the lowest possible power consumption can be guaranteed, even when there is a continuous dominant level on pins lin and txd. 7.2.3 standby mode standby mode is activated automatically when a local or remote wake-up event occurs while the TJA1029 is in sleep mode. in standby mode, pin rxd is held low to provide an interrupt flag fo r the microcontroller. 7.2.4 normal mode in normal mode, the TJA1029 can transmit and receive data via the lin bus. the receiver detects the data stream on the lin bus input pin and transfers it via pin rxd to the microcontroller (see figure 6 ): high for a recessive level and low for a dominant level on the bus. the receiver has a supply -voltage related threshol d with hysteresis and an integrated filter to suppress bus line noise. the transmitter converts the transmit data stream from the protocol controller, detected on pin txd, into an optimized bus signal. the optimized bus signal is shaped to minimize eme. the lin bus output pin is pulled high vi a an internal slave termination resistor. for a master application, connect an external resistor in series with a diode between pin v bat and pin lin (see figure 6 ). if pin slp_n is pulled high while the TJA1029 is in sleep or standby mode, the lin transceiver switches to normal mode after t gotonorm .
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 8 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 7.3 transceiver wake-up 7.3.1 remote wake-up via the lin bus a falling edge on pin li n, followed by a low level maintained for t wake(dom)lin , followed by a rising edge on pin lin, triggers a remote wake-up (see figure 4 ). note that the time period t wake(dom)lin is measured either in normal mode while txd is high, or in sleep mode irrespective of the status of pin txd. 7.3.2 wake-up via pin slp_n if slp_n is held high for t gotonorm , the TJA1029 switches from sleep mode to normal mode. 7.4 operation during automotive cranking pulses TJA1029 remains fully operational during automotive cranking pulses because the lin transceiver is fully specified down to v bat = 5 v. 7.5 operation when supply voltage is outside specified operating range if v bat > 18 v or v bat < 5 v, the TJA1029 may remain operational, but parameter values cannot be guaranteed to remain within the operating ranges specified in ta b l e 7 and ta b l e 8 . if the voltage on pin v bat drops below the low-level power-on reset threshold, v th(por)l , the TJA1029 switches to reset mode. all output drivers are disabled and all inputs are ignored. the TJA1029 switches to sleep mode if v bat > v th(por)h . in normal mode: ? if the input level on pin txd is high, t he lin transmitter output on pin lin will be recessive. ? if the input level on pin lin is recessive, the receiver output on pin rxd will be high. ? if the voltage on pin v bat rises to 27 v (e.g. during an automotive jump-start), the total lin network pull-up resistance should be greater than 680 ? and the total lin network capacitance should be less than 6.8 nf to ensure reliable lin data transfer. fig 4. remote wake-up behavior 015aaa241 lin recessive lin dominant sleep mode standby mode v busdom v busrec ground v lin t wake(dom)lin
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 9 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout ? if the voltage on pin v bat drops below the low-level v bat low threshold, v th(vbatl)l , the lin transmit path is interrupted and the lin output remains recessive. the lin transmit path is switched on again when v bat rises above v th(vbatl)h and the input to pin txd is recessive. 7.6 txd dominant time-out function an initial txd dominant check prevents the bus line being driven to a permanent dominant state (blocking all network communications) if pin txd is forced permanently low by a hardware and/or software applicati on failure. the txd inpu t level is checked after a transition to normal mode. if txd is low, the transmit path remains disabled and is only enabled when txd goes high. once the transmitter has been enabled, a txd dominant time-out timer is started every time pin txd goes low. if the low state on pin txd persists for longer than the txd dominant time-out time (t to(dom)txd ), the transmitter is disabled, releasing the bus line to recessive state. the txd dominant time-out timer is reset when pin txd goes high. 7.7 fail-safe features a pull-down to gnd on pin txd forces a predefined level on the transmit data input if the pin is disconnected. a pull-down to gnd on pin slp_ n forces the transceiver into sleep mode if pin slp_n is disconnected. pin rxd is set floating if v bat is disconnected. the current in the transmitter output stage is limited in order to protect the transmitter against short circuits to pins v bat or gnd. a loss of power (pins v bat and gnd) has no impact on the bus line or on the microcontroller. no reverse currents flow from the bus into pin lin. the current path from v bat to lin via the integrated lin slave termination resistor remains. the lin transceiver can be disconnected from the power supply without influencing the lin bus. the output driver on pin lin is protected against overtemperature conditions. if the junction temperature exceeds the shutdown junction temperature, t j(sd) , the thermal protection circuit disables the output driver. the driver is ena bled again when the junction temperature falls below t j(sd) and pin txd is recessive.
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 10 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 8. limiting values [1] equivalent to discharging a 150 pf capacitor through a 330 ? resistor. [2] equivalent to discharging a 100 pf capacitor through a 1.5 k ? resistor. [3] equivalent to discharging a 200 pf capacitor through a 10 ? resistor and a 0.75 ? h coil. [4] junction temperature in accordance with iec 60747-1. an alternative definition is: t j =t amb +p? r th(j-a) , where r th(j-a) is a fixed value. the rating for t vj limits the allowable combinations of power dissipation (p) and ambient temperature (t amb ). 9. thermal characteristics table 5. limiting values in accordance with the absolute maximum rating system (i ec 60134). all voltages are referenced to pin gnd, unless otherwise specified. positive currents flow into the ic. symbol parameter conditions min max unit v bat battery supply voltage ? 0.3 +42 v v txd voltage on pin txd ? 0.3 +7 v v rxd voltage on pin rxd ? 0.3 +7 v v slp_n voltage on pin slp_n ? 0.3 +7 v v lin voltage on pin lin with respect to gnd and v bat ? 42 +42 v v esd electrostatic discharge voltage according to iec 61000-4-2 on pins lin and v bat [1] ? 8+8 kv human body model on pins lin and v bat [2] ? 8+8 kv on pins txd, rxd and slp_n [2] ? 2+2 kv charge device model all pins ? 750 +750 v machine model all pins [3] ? 200 +200 v t vj virtual junction temperature [4] ? 40 +150 ?c t stg storage temperature ? 55 +150 ?c table 6. thermal characteristics according to iec 60747-1. symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient so8 package; in free air 145 k/w hvson8 package; in free air 50 k/w
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 11 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 10. static characteristics table 7. static characteristics v bat = 5 v to 18 v; t vj = ? 40 ? c to +150 ? c; r l(lin-vbat) = 500 ? ; all voltages are referenced to pin gnd; positive currents flow into the ic; typical values are given at v bat = 12 v; unless otherwise specified. [1] symbol parameter conditions min typ max unit supply v bat battery supply voltage 5 - 18 v i bat battery supply current sl eep mode; bus recessive; v lin =v bat ; v slp_n =0v 2.5 7 10 ? a sleep mode; bus dominant; v lin = 0 v; v bat = 12 v; v slp_n =0v 150 400 1200 ? a standby mode; bus recessive; v lin =v bat ; v slp_n =0v 2.5 7 10 ? a standby mode; bus dominant; v lin = 0 v; v bat = 12 v; v slp_n =0v [2] 100 300 1000 ? a normal mode; bus recessive; v lin =v bat ; v slp_n =5v; v txd =5v 200 800 1600 ? a normal mode; bus dominant; v txd =0v; v slp_n =5v; v bat = 12 v 124ma undervoltage reset v th(por)l low-level power-on reset threshold voltage power-on reset 1.6 3.1 3.9 v v th(por)h high-level po wer-on reset threshold voltage 2.3 3.4 4.3 v v hys(por) power-on reset hysteresis voltage [2] 0.05 0.3 1 v v th(vbatl)l low-level v bat low threshold voltage 3.9 4.4 4.7 v v th(vbatl)h high-level v bat low threshold voltage 4.2 4.7 4.9 v v hys(vbatl) v bat low hysteresis voltage [2] 0.15 0.3 0.6 v pins txd and slp_n v ih high-level input voltage 2 - 7 v v il low-level input voltage ? 0.3 - +0.8 v v hys hysteresis voltage [2] 50 200 400 mv r pd pull-down resistance on txd 50 125 325 k ? on slp_n 100 250 650 k ? pin rxd (open-drain) i ol low-level output current v rxd =0.4v 2 - - ma i lh high-level leakage current [2] ? 5- +5 ? a
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 12 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout [1] all parameters are guaranteed over the virtual junction temperat ure range by design. factory testing uses correlated test co nditions to cover the specified temperature and power supply voltage range. [2] not tested in production; guaranteed by design. pin lin i bus_lim current limitation for driver dominant state v bat =18v; v lin =18v; v txd =0v 40 - 100 ma i bus_pas_dom receiver dominant input leakage current including pull-up resistor v bat = 12 v; v lin = 0 v; v txd = 5 v [2] ? 600 - - ? a i bus_pas_rec receiver recessive input leakage current v bat = 5 v; v lin = 18 v; v txd = 5 v [2] -01 ? a i bus_no_gnd loss-of-ground bus current v bat =18v; v lin =0v [2] ? 750 - +10 ? a i bus_no_bat loss-of-battery bus current v bat =18v; v lin =18v [2] --1 ? a v busdom receiver dominant state - - 0.4v bat v v busrec receiver recessive state 0.6v bat -- v v bus_cnt receiver center voltage v bus_cnt = (v busdom + v busrec )/2 0.475v bat 0.5v bat 0.525v bat v v hys receiver hysteresis voltage v hys = v busrec ? v busdom - - 0.175v bat v v serdiode voltage drop at the serial diode in pull-up path with r slave ; i serdiode =0.9ma [2] 0.4 - 1.0 v v o(dom) dominant output voltage normal mode; v txd = 0 v; v bat = 7.0 v [2] --1 . 4v normal mode; v txd = 0 v; v bat = 18 v [2] --2 . 0v r slave slave resistance 20 30 60 k ? c lin capacitance on pin lin with respect to gnd [2] --2 0p f thermal shutdown t j(sd) shutdown junction temperature [2] 150 - 200 ?c table 7. static characteristics ?continued v bat = 5 v to 18 v; t vj = ? 40 ? c to +150 ? c; r l(lin-vbat) = 500 ? ; all voltages are referenced to pin gnd; positive currents flow into the ic; typical values are given at v bat = 12 v; unless otherwise specified. [1] symbol parameter conditions min typ max unit
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 13 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 11. dynamic characteristics [1] all parameters are guaranteed over the virtual junction temperat ure range by design. factory testing uses correlated test co nditions to cover the specified temperature and power supply voltage ranges. [2] . variable t bus(rec)(min) is illustrated in the lin timing diagram in figure 5 . table 8. dynamic characteristics v bat = 5 v to 18 v; t vj = ? 40 ? c to +150 ? c; r l(lin-vbat) = 500 ? ; all voltages are referenced to pin gnd; positive currents flow into the ic; typical values are given at v bat = 12 v, unless otherwise specified. [1] symbol parameter conditions min typ max unit duty cycles ? 1 duty cycle 1 v th(rec)(max) = 0.744 ? v bat ; v th(dom)(max) = 0.581 ? v bat ; t bit = 50 ? s; v bat =7vto18v [2] [4] [5] 0.396 - - v th(rec)(max) =0.768 ? v bat ; v th(dom)(max) = 0.6 ? v bat ; t bit = 50 ? s; v bat =5vto7v [2] [4] [5] 0.396 - - ? 2 duty cycle 2 v th(rec)(min) = 0.422 ? v bat ; v th(dom)(min) = 0.284 ? v bat ; t bit =50 ? s; v bat =7.6vto18v [3] [4] [5] --0.581 v th(rec)(min) = 0.405 ? v bat ; v th(dom)(min) = 0.271 ? v bat ; t bit =50 ? s; v bat = 5.6 v to 7.6 v [3] [4] [5] --0.581 ? 3 duty cycle 3 v th(rec)(max) = 0.778 ? v bat ; v th(dom)(max) = 0.616 ? v bat ; t bit =96 ? s; v bat =7vto18v [2] [4] [5] 0.417 - - v th(rec)(max) = 0.805 ? v bat ; v th(dom)(max) = 0.637 ? v bat ; t bit =96 ? s; v bat =5vto7v [2] [4] [5] 0.417 - - ? 4 duty cycle 4 v th(rec)(min) = 0.389 ? v bat ; v th(dom)(min) = 0.251 ? v bat ; t bit =96 ? s; v bat =7.6vto18v [3] [4] [5] --0.590 v th(rec)(min) = 0.372 ? v bat v th(dom)(min) = 0.238 ? v bat t bit =96 ? s; v bat = 5.6 v to 7.6 v [3] [4] [5] --0.590 timing characteristics t rx_pd receiver propagation delay rising and falling; c rxd = 20 pf; r rxd = 2.4 k ? [5] --6 ? s t rx_sym receiver propagation delay symmetry c rxd = 20 pf; r rxd = 2.4 k ? ; rising edge with respect to falling edge [5] ? 2- +2 ? s t wake(dom)lin lin dominant wake-up time sleep mode 30 80 150 ? s t gotonorm go to normal time time period for mode change from sleep or standby mode to normal mode 2610 ? s t init(norm) normal mode initialization time 7- 20 ? s t gotosleep go to sleep time time period for mode change from normal to sleep mode 2610 ? s t to(dom)txd txd dominant time-out time timer started at falling edge on txd 6 12 50 ms ? 1 ? 3 ? t bus rec ?? min ?? 2t bit ? ------------------------------- =
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 14 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout [3] . variable t bus(rec)(max) is illustrated in the lin timing diagram in figure 5 . [4] bus load conditions: c bus = 1 nf and r bus =1k ? ; c bus = 6.8 nf and r bus = 660 ? ; c bus = 10 nf and r bus = 500 ? . [5] see timing diagram in figure 5 . ? 2 ? 4 ? t bus rec ?? max ?? 2t bit ? -------------------------------- = fig 5. timing diagram of lin transceiver duty cycle v txd t bit t bit v th(rec)(max) v th(dom)(max) v th(rec)(min) v th(dom)(min) thresholds of receiving node 1 thresholds of receiving node 2 lin bus signal v bat receiving node 1 receiving node 2 v rxd v rxd t rx_pdf 015aaa237 t rx_pdf t rx_pdr t rx_pdf t rx_pdf t rx_pdr t bus(rec)(min) t bus(dom)(max) t bus(rec)(max) t bus(dom)(min)
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 15 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 12. application information 12.1 application diagram 12.2 esd robustness according to lin emc test specification esd robustness (iec 61000-4-2) has been tested by an external test house according to the lin emc test specification (part of c onformance test specification package for lin 2.1, october 10th, 2008). the test report is available on request. 12.3 hardware requirements for lin inte rfaces in automotive applications the TJA1029 satisfies the "hardware requirem ents for lin, can and flexray interfaces in automotive applications", version 1.3, may 2012. 13. test information 13.1 quality information this product has been qualified to the appropriate automotive electronics council (aec) standard q100 or q101 and is suitable for use in automotive applications. (1) master: c = 1 nf; slave: c = 220 pf fig 6. application diagram 015aaa358 1 k v bat lin bus line only for master node lin (1) 7 5 1 4 26 TJA1029 v dd gnd tx0 px.x rx0 txd slp_n rxd micro- controller battery +3 v/ +5 v v ecu table 9. esd robustness (iec 61000-4-2) according to lin emc test specification pin test configuration value unit lin no capacitor connected to lin pin ? 12 kv 220 pf capacitor connected to lin pin ? 12 kv v bat 100 nf capacitor connected to v bat pin > ?14? kv
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 16 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 14. package outline fig 7. package outline sot96-1 (so8) unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 1.0 0.4 sot96-1 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.05 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 99-12-27 03-02-18
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 17 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout fig 8. package outline sot782-1 (hvson8) references outline version european projection issue date iec jedec jeita sot782-1 - - - - - - sot782-1_po 09-08-25 09-08-28 unit (1) mm max nom min 1.00 0.85 0.80 0.05 0.03 0.00 0.2 3.10 3.00 2.90 2.45 2.40 2.35 3.10 3.00 2.90 0.65 1.95 0.45 0.40 0.35 0.1 a dimensions note 1. plastic or metal protrusions of 0.075 maximum per side are not included. hvson8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm sot782-1 a 1 b 0.35 0.30 0.25 cdd h ee h 1.65 1.60 1.55 ee 1 k 0.35 0.30 0.25 lv 0.1 w 0.05 y 0.05 y 1 0 1 2 mm scale mo-229 x c y c y 1 detail x a c a 1 b a d e terminal 1 index area b d h l e h k e 1 e ac b v c w 1 4 8 5 terminal 1 index area
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 18 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 15. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 16. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 16.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 16.3 wave soldering key characteristics in wave soldering are:
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 19 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 16.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 9 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 0 and 11 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 9 . table 10. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 11. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 20 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 17. soldering of hvson packages section 16 contains a brief introduction to the te chniques most commonly used to solder surface mounted devices (smd). a more detailed discussion on soldering hvson leadless package ics can be found in the following application notes: ? an10365 ?surface mount reflow soldering description? ? an10366 ?hvqfn application information? msl: moisture sensitivity level fig 9. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 21 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 18. revision history table 12. revision history document id release date data sheet status change notice supersedes TJA1029 v.1 20130108 product data sheet - -
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 22 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 19.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 19.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
TJA1029 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 8 january 2013 23 of 24 nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comp lete, exhaustive or legally binding. 19.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 20. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors TJA1029 lin 2.2a/sae j2602 transceiver with txd dominant timeout ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 8 january 2013 document identifier: TJA1029 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 lin 2.x/sae j2602 compliant . . . . . . . . . . . . . . 5 7.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . 5 7.2.1 reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2.3 standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2.4 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.3 transceiver wake-up . . . . . . . . . . . . . . . . . . . . 8 7.3.1 remote wake-up via the lin bus . . . . . . . . . . . 8 7.3.2 wake-up via pin slp_n . . . . . . . . . . . . . . . . . . 8 7.4 operation during automotive cranking pulses . 8 7.5 operation when supply voltage is outside specified operating range . . . . . . . . . . . . . . . . . 8 7.6 txd dominant time-out function . . . . . . . . . . . . 9 7.7 fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 9 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 9 thermal characteristics . . . . . . . . . . . . . . . . . 10 10 static characteristics. . . . . . . . . . . . . . . . . . . . 11 11 dynamic characteristics . . . . . . . . . . . . . . . . . 13 12 application information. . . . . . . . . . . . . . . . . . 15 12.1 application diagram . . . . . . . . . . . . . . . . . . . . 15 12.2 esd robustness according to lin emc test specification . . . . . . . . . . . . . . . . . . . . . . . . . . 15 12.3 hardware requirements for lin interfaces in automotive applications . . . . . . . . . . . . . . . . . 15 13 test information . . . . . . . . . . . . . . . . . . . . . . . . 15 13.1 quality information . . . . . . . . . . . . . . . . . . . . . 15 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 15 handling information. . . . . . . . . . . . . . . . . . . . 18 16 soldering of smd packages . . . . . . . . . . . . . . 18 16.1 introduction to soldering . . . . . . . . . . . . . . . . . 18 16.2 wave and reflow soldering . . . . . . . . . . . . . . . 18 16.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 16.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 17 soldering of hvson packages. . . . . . . . . . . . 20 18 revision history . . . . . . . . . . . . . . . . . . . . . . . 21 19 legal information . . . . . . . . . . . . . . . . . . . . . . 22 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 19.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 19.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 22 19.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 23 20 contact information . . . . . . . . . . . . . . . . . . . . 23 21 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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